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Marching Towards The
Core: Board Level Platforms Enter The Network
BY RON KENNEDY
[Go right to Call
Density In Carrier-Grade Systems]
Bigger, better, faster: few casual observers back
in the early 1990s might have thought that those three
simple words would be used to describe the evolution
of board level platforms into the new millennium.
After all, CTI back then still struggled for mind and
market share. Some CPE environments ran small
four-port voice mail systems as an adjunct to the
on-premises PBX. Many network managers, however,
couldn't be convinced to even try out the new computer
telephony paradigm. Application developer needs in
most cases could therefore be met with single DSP
analog boards capable of supporting 10 to 100
simultaneous users, depending on the service.
Yet commercial board level platforms today are
quickly evolving on several fronts. Driven by demands
from emerging competitive service provider markets,
densities and scalability are orders of magnitude
higher than just a few short years ago. IP
connectivity is also becoming much more central. As
well, eight years ago standard DSPs could perhaps run
a single IVR application over 12 channels. This is
also growing by an order of magnitude, to the point
where DSPs can now run multiple applications over 256
channels and more, with onboard co-processors or ASICs
(Application Specific Integrated Circuits) providing
functionality such as TDM-to-IP conversion.
Board quality and reliability are also beginning to
approach the expectations of many "five-nines"
customers with the emergence of CompactPCI
technologies and standards. The more recent emergence
of Compact Packet Switched Backplane (PSB)
technologies will move this even further ahead, and
help drive system-wide scalability into the hundreds
of thousands of customers.
Time To Advance
Board level platforms that form the heart of CT
systems are taking on many of the characteristics
required within the very core of service provider
networks. Vendors in the new ASP, CLEC, and voice
portal markets are increasingly turning to CT systems
as a way to cost effectively and quickly differentiate
their services while gaining a leg up in fiercely
competitive environments. The original promise of the
Advanced Intelligent Network (AIN -- the SS7 network)
of seamless and easy service creation is coming to
fruition in a commercial standards-based form factor.
This trend will likely reach its next logical
plateau over the next two to three years with the
emergence of an increasingly ubiquitous
softswitch-based network. Commercial board level
platforms will have transitioned from running small
voice mail systems in CPE environments ten years ago,
to running CO adjunct systems hanging off the SS7
network today, to running the functionalities of the
traditional proprietary telco switches at the heart of
the softswitch network in the very near term.
Central to this paradigm shift will be continued
advancements in signal processing technology.
Developments in DSP horsepower, smaller footprint
packaging, and reductions in power dissipation will
all help improve overall system scalability while
reducing costs. Increased processing in particular can
translate into cleaner signals, better compression, or
more voice or modem channels per chip.
Arm-In-Arm
But DSP chips no longer have the signal-processing
world to themselves. Today, designers can readily add
some of the key DSP building-block functions and
instructions to devices ranging from low-cost
general-purpose micro-controllers to the latest
generation of x86 and RISC (Reduced Input Set
Computer) CPUs. Specialty architectures, such as
vector processors that conduct
single-instruction/multiple-data (SIMD) operations and
very-long-instruction-word (VLIW) processors, can
perform many operations in parallel. These powerful
architectures also are being used in signal-processing
applications.
The initial attempt to perform DSP-like functions
on general-purpose processors like the Intel Pentium
resulted in mediocre performance thanks to low clock
rates. But today's high internal clock rates (up to
900 MHz in a few cases) and the addition of a few key
features -- such as single-cycle
multiplier-accumulators, improved floating-point
units, and some signal-/image-processing instructions --
make newer processors worthy competitors to
traditional DSPs. And with the addition of dedicated
vector coprocessors that can perform SIMD operations,
RISC CPUs can now surpass the performance of all but
the most advanced DSP chips.
Whether through DSPs or newer variants of CPUs,
more processing power will soon be available to help
effectively deliver many types of next-generation
applications such as voice over IP (VoIP). Of equal
importance to many next-generation service providers
will be the ability to squeeze as much capacity as
possible out of each chassis. Standard port densities
now reach 24 analog lines or 8 T1/E1 spans, with 16
spans a near possibility for some cPCI cards. The next
logical step in the form of T3 boards is now emerging,
with each port providing carriers the equivalent
throughput of 28 T1s. Dual T3 cards that are fully
VoIP capable should be more than able to handle up to
670 active simultaneous users. Dual OC3 boards in the
future hold out the possibility of supporting 4,600
users.
Into The Core
At the heart of service provider needs for highly
scalable, cost-effective, robust board architectures
for the next-generation public network is the
requirement to do away with the static allocation of
CPU resources, voice processing capabilities, and
individual ports to each and every CTI application.
Such traffic engineering calculations were essential
just a few short years ago. Service providers that
wanted to deploy CTI applications running on board
level platforms would need to first gaze into their
mystical crystal ball. They could then arrive at a
complex series of "best guess" estimates as to how
many customers would need what kind of access to how
many applications at any given point in the day. These
numbers would then allow engineers to bang resources
into each and every card. Changes in demand for one
application over another, of course, threw this entire
cumbersome architecture off balance. This
inflexibility makes it totally unsuitable for the
hosted application service model.
Telecom board architectures today essentially
deliver full flexibility at a multi-chassis level to
shift and share resources on the fly. For hosted
application service providers, this means that CTI
systems within large centers can be designed to scale
in all dimensions of an application over multiple
hardware platforms. The same system within smaller
centers can also be collapsed into a single chassis,
while still preserving the same feature-rich suite of
services and potential scalability. From an
application standpoint, system-wide resources within
this architecture appear almost as a virtual pool
running across multiple CTI chassis.
Onto The Backplane
Where this reaches its true potential is with the
emergence of a specification called Compact Packet
Switched Backplane (cPSB). This new telecom bus
architecture basically maps existing switched
Ethernet/IP networks directly onto the backplane of
each CTI chassis. An end-to-end IP architecture offers
significant cost and system integration advantages
over other technologies like ATM an inter-chassis
connect schemes. Standards such as RSVP and MPLS both
offer a way to achieve this. Both have attracted
substantial industry resources, time, and effort over
the past several years.
The concepts of pooling and backhauling DSP
resources are not new. Board level platforms on the
market today are built from the ground up to fully
accommodate these architectures. Such systems can
currently allow up to 256 voice channels to be pushed
across a telecom bus and another 256 channels pulled
across an internal switching fabric to a maximum of 8
T1 spans -- all on the same telecom card. This allows
developers to build extremely dense CTI systems with
all the built-in redundancy inherent to resource
sharing. Hardware costs and system complexities are
substantially reduced, while overall internal
scalability is increased. A ubiquitous internal and
external IP bus architecture based on cPSB technology
will enhance the scalability of this optimized CTI
infrastructure into the tens of thousands of ports
range.
The cPSB specification is still not well defined,
although appears to have the blessing of some of the
industry's heaviest hitters. Spearheaded by
Performance Technologies, an industry consortium is
targeting mid 2001 for fast track ratification of a
cPSB standard as an extension to the PICMG 2.x family
of specifications. The proposed changes are expected
to retain many of cPCI's attributes, as well as
leaving the H.110/H.100 buses intact for systems that
support those standards. This type of model will
enable the creation of integrated systems in which any
card can reside in any link slot and run any operating
system, provided that each card supports standard
Ethernet protocol interfaces. Product time-to-market
can be improved since integration occurs at the system
level rather than at the driver level.
One way to ensure that systems can evolve over time
might be to include both the H.110/H.100 and cPSB
pin-outs on the same resource card. This would offer
maximum interoperability and resource sharing between
systems. H.110-based resources could also access the
faster bus architecture by simply crossing a
card-level switching fabric to a larger GigX on-card
switch.
Aside from the intriguing media convergence
possibilities, this emerging architecture will help
further fuel the rapid adoption of CT platforms into
large scale hosted applications and central office
environments. This should prove especially true again
for the emerging softswitch market, where telephony
systems that are increasingly more dependable,
smaller, and cheaper to own and use will quickly
become an industry imperative.
Ron Kennedy is VP of marketing at Pika
Technologies. For more information, please visit www.pikatech.com.
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