Feature Article
December 2001
 

The Right Tool: Next-Gen Data Transport Architectures

BY BRIAN CARR

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There’s an old adage that says: always use the right tool for the job. It’s just common sense — you get the job done more quickly and with better results, and it’s often the difference between a job done, for example, by a professional builder and the same job done by an enthusiastic homeowner. Many column inches have already been written about the next-generation converged network and the need for network and service to evolve to embrace packet protocols. The dominant protocol — in the access, edge, and core portions of the network — will eventually be the Internet protocol (IP). However, where voice communications is concerned, IP still has a way to go. There are still significant quality of service (QoS) issues to be ironed out, issues that are already addressed and mostly solved by ATM. This gives ATM a prominence in existing implementations, particularly in the mobile communications sector, which guarantees ATM can expect to be an important technology for a long time yet.

Open standards are able to help accelerate the development of converged network equipment, and CompactPCI has quickly established itself as a leading open-standards choice for multiple-card telecom applications. The PCI Industrial Computer Manufacturers Group (PICMG), which manages the standard, has moved quickly to establish advanced inter-card data transport mechanisms as required to help support the evolution of applications.

This article examines how these various open standards apply to the real demands of next-generation equipment and considers whether they are sufficient in themselves to help meet the needs: to be the right tools for the job.

The Computer Telephony Bus Extension (H.110)
The H.110 computer telephony bus extension is designed to carry voice calls between cards in a chassis in the same 64 Kbps time-division-multiplexed (TDM or timeslot) form that they are received from the public telephone network (PSTN).

The concept is simple and scaleable. Voice calls are terminated on dedicated line termination cards and are routed via the H.110 bus to a range of additional voice processing or DSP resource cards that perform specific functions under the control of a service application. 

When voice over IP applications such as VoIP trunking and access gateways began to be considered, it was natural to use the same basic data flow architecture. However, the CompactPCI bus is not suited for aggregating packet voice flows. Including the packet processing and packet network interface on the DSP resource card solves this. Each such packet voice resource board then has a separate redundant 100 Mbps Ethernet link for the packet data stream that, for larger installations, is aggregated upstream in an external Ethernet switch.

The limitation of H.110 bus timeslots remains a serious issue for scalability — particularly for high-density packet voice gateways that are intended to support many thousands of users. The H.110 bus is limited to 4,096 timeslots, supporting only 2,048 users. One way to address this limitation is to remove the need for H.110 entirely by provisioning each packet voice resource board with a suitable line termination and sufficient DSP and packet processing resources to process all channels. This processor blade approach solves the problem without resorting to the extra expense and backplane designs for an H.110 segmentation approach, but does mean that each card should do everything required by the application.

Packet Switched Backplane Extension
Having addressed the limitation on scalability for IP connected systems, larger and larger VoIP gateways could be constructed by using more and more cards. With each card requiring Ethernet links to both redundant external Ethernet switches, the cabling and space required for the external Ethernet switches has come under scrutiny. The result was simplicity itself — to bring the multiple redundant Ethernet links and aggregation switches inside the chassis. This is the premise behind the CompactPCI Switched Backplane (CPSB), now standardized as PICMG 2.16.

CPSB has two dedicated fabric switch cards in a shelf. Each peripheral node is linked directly to each fabric using traces that can support 10/100/1000 BaseT Ethernet. Each switch fabric is designed to perform aggregation and switch/routing for the entire chassis and features gigabit Ethernet connections to a LAN/WAN.

CPSB is complementary to H.110 — it means that both H.110 architecture systems and all-in-one packet voice resource boards work equally well. It also means that multiple processor clusters are capable of being easily implemented, supporting applications like database servers and cellular home and visitor location registers (HLR/VLR).

Furthermore, the native Ethernet link to each card slot has another advantage that is expected to become more important in the next year or so: that of improving high availability by replacing the CompactPCI bus as the primary means of application control.

Considerations For HA
Despite the CompactPCI bus standard beginning the drive towards open standards-based HA systems, it is actually the bus itself and the accompanying driver architectures that are now perceived as barriers to achieving higher availability. Any single bus must be considered as a single point of failure in a system and so must either be duplicated or eliminated. Duplication of the PCI bus across a large chassis with multiple bridging is much more complex than elimination, but until recently, standards to replace the capability of PCI to manage both low-level hardware and higher level software did not exist.

A standard for low-level hardware management evolved from efforts by Intel in the desktop and server PCI space to develop the IPMI management bus. This was brought into the CompactPCI arena as the PICMG 2.9 standard. Across the management bus, each card slot is able to be interrogated and controlled independently without recourse to the PCI bus. When implemented as a star topology with a link to each card, the management bus itself is not a single point of failure.

The missing link was application level control. However, with the advent of PICMG 2.16, each card is now connected to a redundant Ethernet network, and so high-level management and command and control can be implemented using a secure IP transport mechanism. The way is clear to remove the actual CompactPCI bus and eliminate this single point of failure — and this mode of operation was specifically supported within PICMG 2.16.

ATM Transport — The Challenge
ATM is required for advanced applications such as voice over DSL gateways and is used heavily in UMTS (3G) wireless elements such as Node B base stations, radio network controllers (RNC), and media gateways (MGW). However, most recent emphasis in the standards arena has focused on improving the data flow architecture for IP communications while keeping the basic telephony handling capabilities of H.110. Nothing yet has addressed the needs of ATM.

This omission may be traced back to the roots of the open standards industry. Until now, most applications for open standards have been in the access network — feature-rich service platforms with relatively few channels. The core switching network elements were predominantly proprietary, and it is in the core network or the network edge that ATM has been most evident. This situation is now being changed first by the network evolution towards all-packet networks (where ATM has already solved all the quality of service issues confronting the all-IP proponents) and second by the growth in the outsourcing business model that leads even core network equipment manufacturers to look to open standards for their next-generation developments. Both aspects are now bringing ATM requirements to the open standards industry.

Currently, the situation is evolving in the same way that CPSB evolved. Rather than aggregating and distributing ATM traffic within a chassis, ATM connections are being taken directly from the cards to external ATM switches. Unfortunately, this is problematic not only from a cabling view. The latest ATM/AAL2 standards allow up to 248 channels to be embedded within a single virtual circuit, but many ATM switches can only make connections to the resolution of a single virtual circuit and so cannot perform individual call switching.

This means that the industry needs to develop a new architecture with the capacity and cell structure of ATM plus the redundancy of CPSB and the per-channel resolution of H.110.

Innovating New Standards
The needs of communications equipment are evolving quickly, and the open standards toolbox is evolving to keep step. Advanced network elements must be capable of packet communications as well as the more traditional timeslot-based voice communications. The growth in the outsourcing business model has meant core network reliability requirements being placed on open standards equipment. New tools are needed.

At a hardware and interface level, this has meant the definition of standards that build on the successful base of CompactPCI to offer timeslot traffic distribution and Ethernet IP packet distribution within a chassis. The new management bus, together with the all-slot IP control that CPSB brings, allows the CompactPCI bus itself to be eliminated. These tools, especially CPSB, are certainly effective for extending traditional computer telephony style applications into the next-generation converged network. However, H.110 has some severe limitations, and there is one crucial tool missing — the one that helps support ATM applications.

For ATM there is no standard underway yet that meets in-chassis aggregation and distribution requirements. Thus it is left to individual innovation to fill the gap, and to provide the right tool for the job.

Brian Carr is telecom product manager, Motorola Computer Group. For more information about Motorola Computer Group, please visit www.mcg.mot.com

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An HA Multi-Service Platform

Motorola Computer Group has taken up the challenge of developing a new architecture in its latest platform architecture — the MXP Multi-Service Packet Transport Platform. The MXP multi-service chassis is designed to offer all the latest features: CPSB, IPMI management, no CompactPCI bus to compromise reliability. Better still, the MXP together with the C-5 based Packet Processing Resource Board offers the capability to handle ATM applications with the same flexibility as TDM and IP applications.

The Multi-Service Packet Transport Platform (MXP) is an embedded telecom applications platform that will help to provide the highest data throughput rate in the industry with the ability to deliver multiple services that can connect to different networks.

Multiple networks enable the MXP to help achieve the performance and throughput necessary to support applications on both the control and data planes:

  • An Intelligent Platform Management Interface (PICMG 2.9) interconnection for combined system and resource management that increases payload by eliminating need for PCI bridging and system slots.
  • A dual-star Ethernet network (PICMG 2.16) connects payload and alarm board slots to an IP switch providing IP board-to-board communications.
  • A high-speed mesh network in place of H.110 that offers another mechanism for data transport. The mesh network carries cell-based traffic that can be any protocol and, in particular, can carry both TDM and ATM traffic at the same time. The high-speed data fabric fills a void not just for bandwidth, but also for protocols and QoS that are not supported by IP.

Together with this new mesh network, Motorola announced a high performance Packet Processor Resource Board based on the C-port C-5 network processor capable of ATM aggregation and ATM/AAL2 switching. This enables all forms of data transport to be brought inside the chassis for maximum flexibility and scalability.